This invention relates to a system of a plurality of devices connected in sequence in a predetermined order where the devices are programmable to receive information in the same order as in the sequence. The system is particularly useful for initializing a number of computer peripheral integrated circuit chips.
The computer system may include a number of stand-alone devices, each of which should be initialized before the system is operated. For example, a computer system may include a number of peripherals which should be initialized. Alternatively, a computer system may comprise a number of stand-alone computers connected together to form a network, where each computer should be initialized. In either case, each stand-alone device has to be initialized before the system can operate.
The initialization process typically includes the loading of data into certain registers in the devices in the system. The process is controlled by a central processing unit (CPU) which accesses each of the stand-alone devices by a certain identifying address unique to such device. When the particular device is accessed for initialization, the CPU provides the data destined for the registers of such device on a bus connected to the devices. In conventional systems, each stand-alone device requires a separate address decoder to identify the identifying address from the access codes provided by the CPU onto the bus. Such decoders usually comprise logic gates hardwired to each device to identify a particular identifying address which cannot be later changed or programmed. Where the stand-alone device is implemented as an integrated circuit, that means an address decoder external to the peripheral integrated circuit is required (unless each device itself is hardwired to identify a particular unalterable address, which is even less desirable). Hence each stand-alone device requires a separate address decoder which increases the number of chips required on printed circuit board assemblies. It is therefore desirable to provide a system whereby a single decoder is adequate for allowing the CPU to access all the stand-alone devices for the purpose of initialization.